Among
the favorite topics of research in the field of information technology is parallel
processing which involves computer networks and network interfaces. In 2000,
the field of NoC or Networks-on-Chip was designed because of the advent of the
multi-core computer processing unit (CPU) and due to the predicted computing
growth towards extremely incorporated design with interconnected networks.
Several surveys have been conducted about NoC and have been published. One of
the leading topics that involve NoC is the fault-tolerant design which is
well-known in terms of its significance and interest of the experts in technology
and computer system.
In order to cope with the fast
growing trend of the computation-intensive application and the need for low
power yet high performance system, several computing resources in single chips
have been invented[1].
This becomes possible because of the presence of the current VLSI technology
which can support an extensive integration of transistors. The presence of
interconnection among several computing resources such as CPU, DSP, specific
IP’s and other resources in System –on-Chip, the interconnection process have
become more challenging[2].
The continuous evolution of new application has become the reason of the
invention of some new processor, memory and accelerator cores. Moreover, the
fast development and improvement of computation and the complexity of
communication have caused the invention of the scalability-centered paradigms.
These are the reasons why network-on-Chip (NoC) is designed in order to be an
alternative in providing high-performing communication system in the field of Systems-on-Chip
(SoCs) with several cores incorporated in one silicon die[3].
The Netwok-on-Chip is an effective
architecture in the communication system under the System-on- Chip. It permits
the incorporation of hefty quantity of computational blocks in a single
circuit. NoC allows the reutilization of blocks which results to the provision
of high degree parallelism and performance of the system in higher level. Accordingly,
the rising demand for NoC is a result of the requirement to achieve higher
bandwidth if the field of communication. As stipulated in Moorse law, the
integration of the transistor can be doubled within the approximate eighteen
months, however, challenges and the competition of the physical connection in
Integrated Circuit (ICs) has caused severity in the delay of connections among
the global wires[4].
The traditional method of connection namely, end-to-end, bus-based and other
are not good solution to the problem regarding the wire delay in integrating IP
cores with System-on-Chips because they do not scale well if there are more mechanism
that are supplied into the system[5]. Moreover, there is the ad hoc solution that
is of varying buses, crossbar and wiring that can attain mainly advantageous
performance especially for specific application. However, the system cannot be
recycled and it requires great costs for its development and verification.
This is where NoC comes in because
it has the potential of providing short circuits and can thereby reduce the
delays in wire. The utilization of NoC replaces the traditional methods of
interconnection and it has several advantages in terms of its performance and
modularity. Furthermore, it was observed that the utilization of NoC among
electrical properties have optimized,
while it has reduced the power consumption ten folds and increased the speed
three times as compared with the system that utilizes the bus-based connection.
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